Power consumption has emerged as a primary design constraint for integratedcircuits (ICs). In the Nano meter technology regime, leakage power has become amajor component of total power. Full adder is the basic functional unit of anALU. The power consumption of a processor is lowered by lowering the powerconsumption of an ALU, and the power consumption of an ALU can be lowered bylowering the power consumption of Full adder. So the full adder designs withlow power characteristics are becoming more popular these days. This proposedwork illustrates the design of the low-power less transistor full adder designsusing cadence tool and virtuoso platform, the entire simulations have been doneon 180nm single n-well CMOS bulk technology, in virtuoso platform of cadencetool with the supply voltage 1.8V and frequency of 100MHz. These circuitsconsume less power with maximum (6T design)of 93.1% power saving compare toconventional 28T design and 80.2% power saving compare to SERF design withoutmuch delay degradation. The proposed circuit exploits the advantage of GDItechnique and pass transistor logic
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